1. Technical Field
The present invention generally relates to integrated circuits (ICs), and more particularly to interconnect structures, including multilevel interconnect structures, in which the internal stress of the structure is significantly reduced by employing a stress adjustment cap layer. The present invention is also directed to a method of fabricating an interconnect structure having a significantly reduced internal stress.
2. Description of Related Art
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit including chips (e.g., chip back end of line, or xe2x80x9cBEOLxe2x80x9d), thin film packages and printed circuit boards. Integrated circuits can be useful for computers and electronic equipment and can contain millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate. For the device to be functional, a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the device. Efficient routing of these signals across the device can become more difficult as the complexity and number of the integrated circuits are increased. Thus, the formation of multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring structures, have become more desirable due to their efficacy in providing high speed signal routing patterns between large numbers of transistors on a complex semiconductor chip. Within the interconnection structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate.
Presently, interconnect structures formed on an integrated circuit chip consists of at least about 2 to 8 wiring levels fabricated at a minimum lithographic feature size designated about 1xc3x97 (referred to as xe2x80x9cthinwiresxe2x80x9d) and above these levels are about 2 to 4 wiring levels fabricated at a width greater than about 1xc3x97 the minimum width of the of the thinwires. Typically, these larger wires have a width equal to about 2xc3x97 and/or about 4xc3x97 the minimum width of the thinwires (referred to as xe2x80x9cfatwiresxe2x80x9d). Fatwires may have any width greater than about 1xc3x97 the minimum width of the thinwires with 2xc3x97 and 4xc3x97 being common examples. In one class of prior art structures, the thinwires are formed in a low dielectric constant (k) organic polymer dielectric layer, and the fatwires are made in a silicon dioxide dielectric layer having a dielectric constant of about 4. See, e.g., Goldblatt, et al., xe2x80x9cA High Performance 0.13 xcexcm Copper BEOL Technology with Low-K Dielectricxe2x80x9d, Proceedings of IITC, 2000.
However, reliability problems are associated with these prior art structures. For example, these structures are not sufficient to withstand present processing operations including the thermal cycling associated with semiconductor manufacturing. Typically, the semiconductor device is subjected to about 5 to 20 thermal cycles to a temperature of 400-450xc2x0 C. during manufacture. Also, during operation in the field, the device is further subjected to a large number of thermal cycles to a temperature of about 150xc2x0 C. The reliability testing of completed IC""s commonly includes a xe2x80x9cthermal cyclexe2x80x9d test in which the part is cycled hundreds of times between a selected low temperature and a selected high temperature. A variety of factors lead to a change in resistance of the metal vias within the interconnect structure when these thermal cycles occurs with the via resistance increasing with repeated thermal cycles. The largest increase in via resistance has been found to occur at the uppermost thinwire layer level below the fatwire layer levels.
Another problem associated with these prior art structures is poor adhesion observed at the location of the interface of the uppermost thinwire level and bottommost fatwire level. Poor adhesion is due to the high stress level of the material in the layers associated with the interface. This phenomenon is known as peeling. The details of this adhesion problem are not yet sufficiently clear or complete to those skilled in the art. It is believed that the problem of poor adhesion exists due to the high stress level of the material in the layers associated with the interface. Each material in these layers exhibits an internal stress, either tensile or compressive, which can eventually cause curving of the layer superimposed on another layer. By convention, tensile stress has a value greater than zero while compressive stress has a value less than zero. If the stress is particularly high so as to generate forces at the interface which are greater than the adhesion forces between the layers, peeling occurs.
It would therefore be desirable to provide an interconnect structure that can provide better adhesion at the interface of the uppermost thinwire and bottommost fatwire levels as well as a relatively low effective capacitance for the device. This allows for electric signals to travel faster therethrough. It would also be desirable for the interconnect structure to possess a substantially low stress level, i.e., one equal to about zero, thereby providing a stable structure when subjected to thermal cycles at both low temperatures, e.g., room temperature, and at high temperatures, e.g., temperatures above about 150xc2x0 C. It would further be desirable to adjust the stress of the structure to relatively low compressive values (not zero) as needed for specific applications.
It is therefore an object of the present invention to provide a BEOL interconnect structure of, e.g., the dual damascene type, with a reduced effective capacitance (i.e., low-k) in both the thinwire and fatwire levels.
It is also an object of the present invention to provide a BEOL interconnect structure of, e.g., the dual damascene type, with improved adhesion.
It is a further object of the present invention to provide a BEOL interconnect structure which includes at least a stress adjustment cap layer formed between a first layer having a coefficient of thermal expansion (xe2x80x9cCTExe2x80x9d) greater than about 20 parts per million (xe2x80x9cppmxe2x80x9d) and a first internal stress associated therewith and a second layer having a CTE less than about 20 ppm and a second internal stress associated therewith wherein the cap layer possesses an internal stress to offset the first internal stress of the first layer and the second internal stress of the second layer. A cap layer having an adjustable stress state (i.e., tensile vs. compressive) can induce a favorable relief of stress on the interconnect structure, i.e., provides an interconnect structure having a substantially low internal stress, e.g., one possessing an internal stress equal to about zero. In this manner, the interconnect structure has improved stress matching stability during thermal cycling.
In keeping with these and other objects of the present invention, there is provided an interconnect structure comprising a first layer having a CTE greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a CTE less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and a stress adjustment cap layer formed between the first layer and the second layer, the cap layer having a third internal stress to offset the first internal stress associated with the first layer and the second internal stress associated with the second layer and induce a favorable relief of stress on the interconnect structure.
Also in accordance with the present invention, an interconnect structure is provided which comprises one or more levels of a first layer having a CTE greater than about 20 ppm and a first set of metallic lines formed therein; one or more levels of a second layer having a CTE less than about 20 ppm and a second set of metallic lines formed therein wherein the width of each of the metallic lines in the first set is equal to or greater than the width of each of the metallic lines in the second set, and a stress adjustment cap layer formed therebetween.
A method for making an interconnect structure having a substantially reduced internal stress useful in forming a semiconductor device has also been discovered which comprises the steps of:
a) forming one or more levels on at least a portion of an integrated chip, each level comprising a first layer having a CTE greater than about 20 ppm and a first internal stress associated therewith, each first layer having a first set of metallic lines formed therein;
b) forming a stress adjustment cap layer on the first layer of the uppermost layer;
c) forming one or more levels on at least a portion of the cap layer, each level comprising a second layer having a CTE less than about 20 ppm and a second internal stress associated therewith, each second layer having a second set of metallic lines formed therein; wherein the cap layer possesses a third internal stress to offset the first internal stress associated with the first layer and the second internal stress associated with the second layer and induce a favorable relief of stress on the interconnect structure.